The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
This disclosure relates generally to data decoding, and more particularly to a hybrid decoder architecture that utilizes primary and secondary decoders with different levels of complexity. While the primary decoder may concurrently decode an entire received codeword, the higher-complexity secondary decoder may sequentially decode the received codeword by breaking it up into two or more codeword portions. In this way, the secondary decoder may be available to decode codewords having a codeword length greater than the maximum codeword length supported by the secondary decoder for concurrent decoding. In some aspects, a class of LDPC codes for which such successive decoding can be supported may be referred to as cascade LDPC codes.
LDPC codes have become an important component of some error-correcting systems. LDPC codes may employ several different kinds of parity check matrices. For example, the structure of an LDPC code's parity check matrix may be random, cyclic, or quasi-cyclic. LDPC codes defined by quasi-cyclic parity check matrices are particularly common and computationally efficient. These codes are known as quasi-cyclic low density parity check (QC-LDPC) codes.
The structure of an LDPC code's parity check matrix may determine what types of decoding algorithms may be used with that LDPC code. For example, for QC-LDPC codes, layered decoding techniques may be used, which exploit the fact that a QC-LDPC code's parity check matrix consists of circular submatrices or so-called “circulants.” The size of these circulants corresponds to the number of check node processors necessary to implement layered decoding and determines to what extent the processing of the parity check matrix can be parallelized. For example, a parity check matrix composed of circulants of size Sc can be implemented using Sc check node processors.
As used herein, the term “message” refers to a numerical value, usually representing a log likelihood ratio (LLR). An LDPC decoder may decode LDPC codes using an iterative message-passing algorithm, such as a min-sum decoding algorithm. Iterative algorithms of this type may decode a received codeword using an iterative process in which each iteration includes two update steps involving check nodes and variable nodes.